Japanese Patent Application Laid-Open Publication No. 2012-195492 (Patent Document 1) describes a technique relating to a power semiconductor module having a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and its mounting structure. This power semiconductor module includes a first metal substrate with a power semiconductor element mounted thereon and a second metal substrate without a power semiconductor element mounted thereon, and has such a structure that a back surface opposite to a power semiconductor element mounting surface of the first metal substrate is exposed outside a resin package to form a heat dissipation surface.
Japanese Patent Application Laid-Open Publication No. 2005-109100 (Patent Document 2) describes a semiconductor device having a power chip and its manufacturing technique. More specifically, in assembly of a semiconductor device described in the Patent Document 2, this document discloses a resin molding technique of placing a resin sheet attached with a metal foil on an inner bottom surface of a resin sealing mold.